Thoughts on the STM32G0 I2C Peripheral Mode

Using RM0444 - dm00371828, for the STM32G0x1 platform

Supports Standard Mode, Fast Mode, and Fast Mode Plus
Has DMA support
Can do multimaster
Can do 7/10 bit addressing
Multiple 7-bit addresses, "2 addresses, 1 with configurable mask"
Supports optional clock stretching

Feature	I2C1	I2C2
7 bit addr	X	X
10 bit addr	X	X
100kbit/s	X	X
400kbit/s	X	X
1Mbit/s	X	X
Independent clock	X
Wakeup from stop	X
SMBus/PMBus	X

32.4.4 talks about clocking requirements.

Probably relevant when doing clock configuration.

32.4.6 talks about initialization

You must config + enable I2C peripheral clock
You enable the I2C by setting PE bit in I2C_CR1 register
When you disable with PE bit, a "software reset" occurs (see 32.4.7)
Analog filter is enabled by default, disabled with ANFOFF bit, or use a digital filter with DNF3..0 in the I2C_CR1 register
Table 164 talks about tradeoffs between analog/digital
- Analog is available in stop mode w/ addr wakeup, digital isn't
- Analog is variable with temp, voltage, etc.
- Digital is programmable
Don't change filter while I2C enabled
Table 165 (and preceding text) talks a LOOOOT about timing calculation. This is probably important, but overwhelming
Don't change the timing while I2C enabled

Figure 287 is a flow chart of initialization steps. Basically:

Turn off I2C_CR1::PE
Configure I2C_CR1::ANFOFF and I2C_CR1::DNF
Configure PRESC, SDADEL, SCLDEL, SCLH, SCLL in I2C_TIMINGR
Configure I2C_CR1::NOSTRETCH
Turn on I2C_CR1::PE

32.4.7 Talks about software reset

It has a list of affected bytes
You need to keep it low for at least 3 APB cycles to do the software reset. They recommend:
- Write PE 0
- Read PE
- Write PE 1

32.4.8 Talks about data transfer

There is a one byte buffer for each direction, shifted in/out.

Receiving

Data is shifted in
On full byte:
- If RXNE=0, then byte is put in I2C_RXDR
- If RXNE=1, then clock is stretched until RXNE=0

Transmitting

Data is shifted out
On empty byte:
- If TXE=0, then byte is copied from I2C_TXDR
- If TXE=1, then clock is stretched until TXE=0

HW Transfer Management

I2C has a byte counter, enabled by default in master, disabled in slave
Controlled through I2C_CR2::SBC bit
Number of bytes for counter is I2C_CR2::NBYTES byte.
Also has a RELOAD bit for generating TCR flag when you need to load more than 255 bytes
You must clear RELOAD on last chunk

When not using RELOAD as a master, you can use AUTOEND to send a stop automatically when transfered. Or you can disable to possibly get a flag/interrupt when you need to START (restart) or STOP w/ software control

Table 166 shows master/slave configurations of SBC, RELOAD, and AUTOEND.

32.4.9 talks about slave mode

You must set at least one address
- Configured with I2C_OAR1 and I2C_OAR2
- OA1 is 7 bit by default, set in OA1MODE in I2C_OAR1
- Enabled by OA1EN in I2C_OAR1 register
- OA2 has masks for matching multiple wildcard'y addresses
- Mask logic is odd, I don't get it yet.
- OA2 is always 7 bit
- OA2 is enabled by setting OA2EN in O2C_OAR2
You can enable General Call address by setting GCEN in I2C_CR1
You can get a flag or interrupt on address match
Usually the slave uses clock stretching. can be disabled
If using wildcard addrs, I2C_ISR::ADDCODE can be checked. Also check DIR for direction
Must clear ADDR flag to release stretch
If you don't stretch, you'll get all kinds of over/underrun error flags set